Solder bump interconnection techniques for both electrically contacting component packages and mounting them on interconnection substrates such as printed circuit boards has become widely used in the manufacture of electronic devices. Interconnection substrates includes several forms of electronic device supports including, e.g., silicon and ceramic. For convenience reference to such supports herein will be to printed wiring boards as a generic term.
State of the art component packages are small and lightweight and can be surface mounted to printed circuit boards using fine patterns of solder bumps. Typically, bumps or pads are formed on both the printed wiring board and the component package in mirror arrays that mate when the component package is properly placed. Assembly is completed by applying heat to melt the solder and form the solder bond and interconnection. This technique is used in flip-chip technology where the surface of the IC chip in the component package is provided with bonding pads or bumps and the chip is mounted upside down on the printed wiring board.
The solder bumps are formed on arrays of I/O contact pads prior to assembly. To facilitate localized or selective application of solder to the array of contact pads the surface of the pads should be solder wettable. The metal interconnection pattern typically used for integrated circuits boards or cards is aluminum. While techniques for soldering directly to aluminum have been tried it is well known and accepted that aluminum is not a desirable material to solder. Consequently the practice in the industry is to apply a metal coating on the aluminum contact pads, and apply the solder bump or pad to the coating. This coating is referred to as under bump metallization (UBM).
The metal or metals used in UBM technology must adhere well to aluminum, be wettable by typical tin solder formulations, and be highly conductive. A structure meeting these requirements is a composite of chromium and copper. Chromium is deposited first, to adhere to the aluminum, and copper is applied over the chromium to provide a solder wettable surface. Chromium is known to adhere well to a variety of materials, organic as well as inorganic. Accordingly it adheres well to dielectric materials, e.g. SiO.sub.2, SINCAPS, polyimide, etc., commonly used in IC processing, as well as to metals such as copper and aluminum. However, solder alloys dissolve copper and de-wet from chromium. Therefore, a thin layer of copper directly on chromium will dissolve into the molten solder and then the solder will de-wet from the chromium layer. To insure interface integrity between the solder and the UBM, a composite or alloy layer of chromium and copper is typically used between the chromium and copper layers.
The aforementioned layers are conventionally sputtered, so several options for depositing them are conveniently available. The layer can be sputtered from an alloy target. It can be sputtered using a chromium target, then changing to a copper target. Or it can be sputtered using separate chromium and copper targets, and transitioning between the two. The latter option produces a layer with a graded composition, and is a preferred technique.
In forming the structure just described the accepted practice is to use an additive process for selective deposition of the composite layer. Additive processes are well known and include lift-off techniques, and the use of shadow masks. Additive processes are used because chromium and copper are not compatible from the standpoint of etch selectivity. It is known that chromium layers readily form an oxide film on exposure to air or water. Chromium oxide is a known refractory material with extreme hardness. To remove this oxide, and etch through the chromium, requires either highly acidic or highly basic etch solutions. Among the known effective etchants for chromium are solutions of hydrated cesium/ammonium sulfate mixed with nitric acid or perchloric acid (HCIO.sub.4). These etching baths are very acidic, with a pH of 1 or 2, and will etch copper at a rate 10-100 times the rate for chromium. Therefore to clear 2000 Angstroms of chromium requires a copper layer substantially in excess of 2 microns. While it is theoretically possible to deposit a thick copper layer and sacrifice a major part of the layer in order to etch through the chromium containing underlayers, control of the thickness of the final copper layer in such an etch mode is very poor, and edge definition suffers considerably.
Typical of the basic etch solutions for chromium is an aqueous mixture of sodium hydroxide and potassium ferricyanide. This solution has a pH of around 13, and is very selective with respect to copper due to the formation of an insoluble film of copper hydroxide on the copper surface. Because of this extreme etch selectivity, this etchant will not etch the copper/chromium mixed layer that is useful for the integrity of the UBM.
For more details on etch solutions for chromium and copper see e.g. Thin Film Processes, Edited by J. L. Vossen, Academic Press, San Diego, pp. 465-467.
Because of the unfavorable etch selectivity of known acidic chemical etchants for chromium/copper composite structures, and because the known basic solutions will not etch a Cu/Cr layer, the conventional approach in the art is to use an additive process for forming the composite layer. These processes do not require etchants for the metal layers. However, additive processes suffer known deficiencies in comparison with substractive processes, e.g. photolithographic patterning. Prominent among those is lack of edge definition and generally inferior resolution. As the size of IC packages continues to shrink, the pitch of I/O contact arrays decreases, thus increasing the need for selective deposition processes with high definition. Accordingly, solder bump technology with under bump metallization would be advanced substantially by a selective deposition process that uses standard lithographic patterning. Such an advance requires the development of an effective etchant for Cu--Cu/Cr--Cr composite layers.